Power metal oxide semiconductor field-effect transistors (MOSFET) are generally used to handle high power levels in comparison to lateral transistors in integrated circuits. FIG. 6 shows a typical MOSFET which uses a vertical diffused MOSFET structure, also called double-diffused MOSFET structure (DMOS or VDMOS).
As shown, for example, in FIG. 6, on an N+ substrate 415 there is a N− epitaxial layer formed whose thickness and doping generally determines the voltage rating of the device. From the top into the epitaxial layer 410 there are formed N+ doped left and right source regions 430 surrounded by P-doped region 420 which forms the P-base. The P-base may have an out diffusion area 425 surrounding the P-base 420. A source contact 460 generally contacts both regions 430 and 420 on the surface of the die and is generally formed by a metal layer that connects both left and right source region. An insulating layer 450, typically silicon dioxide or any other suitable material, insulates a polysilicon gate 440 which covers a part of the P-base region 420 and out diffusion area 425. The gate 440 is connected to a gate contact 470 which is usually formed by another metal layer. The bottom side of this vertical transistor has another metal layer 405 forming the drain contact 480. In summary, FIG. 6 shows a typical elementary cell of a MOSFET that can be very small and comprises a common drain, a common gate and two source regions and two channels. Other similar cells may be used in a vertical power MOSFET. A plurality of such cells may generally be connected in parallel to form a power MOSFET.
In the On-state, a channel is formed within the area of regions 420 and 425 covered by the gate reaching from the surface into the regions 420 and 425, respectively. Thus, current can flow as indicated by the horizontal arrow. The cell structure must provide for a sufficient width d of gate 440 to allow for this current to turn into a vertical current flowing to the drain side as indicated by the vertical arrows.
Such structures have a relatively high gate source capacitance due to the necessary width of the gate which is undesirable, in particular, in high frequency switching applications such as switched mode power supplies.